In recent years, the density of components that is integrated into single integrated circuit design has increased at a high rate. Example of such high density circuits include dynamic random access memories DRAMS, which are now being fabricated at 16 megabit single-chip densities. In order to accomplish such complexities while maintaining the size of the chip at reasonable and manufacturable levels, the minimum feature size transistors and other components must of course be reduced For DRAM devices which have generally been the most densely integrated devices in the industry, the size of features such as MOS transistor gates is generally at the smallest size manufacturable by available technology. In the example of 16 MBIT DRAM devices, transistor gate lengths are expected to be in the range of 0.5 to 0.7 microns.
It is well known that MOS transistors which have gate widths and accordingly transistor channel lengths which are of sub-micron dimensions are subject to time and voltage dependent phenomena to which larger transistors are not subject. An example of such phenomena is transistor performance degradation due to channel hot-carrier effects. While certain techniques are available to reduce the susceptibility of transistors to channel hot-carrier effects, such as providing graded junctions as described in U.S. Pat. No. 4,356,623 issued and assigned to Texas Instruments Incorporated, the drain to source voltage nominally applied to the transistor structure remains a strong factor in the channel hot-carrier degradation of the transistor performance.
Further, the storage element in DRAMS is commonly a thin film capacitor. It is well known that the data stored in DRAM capacitors may be upset by naturally occurring alpha particles. The degree to which data is lost in such events depends upon a capacitance of the memory cell and accordingly the capacity of modern DRAM cells is generally maintained above 35 fF for each cell and preferably above 50 fF. Since it is desirable that the density of storage cells per unit area should be as large as possible, in order to maintain the necessary storage capacitance of 35 to 50 fF, the thickness of the capacitor dielectric must be reduced. Modern storage capacitors have dielectric thicknesses on the order of the equivalent 10 nm of silicon dioxide or less. However, with such thin capacitor dielectrics, both dielectric breakdown voltage and time-dependent dielectric breakdown rates degrade with thinner dielectrics, assuming a constant voltage applied there across.
For these reasons, the power supply voltage applied to such high density VLSI devices including DRAMS, other memories and logic devices are preferably reduced as the feature sizes decrease. In addition, since the power dissipation of the chip increases with increasing number of components integrated into the chip, a reduced power supply voltage would also reduce the power supply dissipation. Many other circuits may still use a higher power supply voltage, for example 5 volts nominally, then it's desired by the high density components described above, for example, 3.3 volts which makes the designer of systems incorporating these devices reluctant to provide an additional power supply in the system, due to the cost of such other supplies and the routing of an additional bias voltage.
It should be noted that it is desirable that the performance of the integrated circuit should not vary strongly with power supply voltage applied thereto, as such variation may increase the cost of production and testing of the chip during its manufacture, but such variation may also cause system-level problems for the user.
Furthermore, in the field of DRAM devices, due to the large amount of tbin capacitor dielectric on each device, manufactures generally perform a "burn-in" operation during the test process of the chips. Burn-in is intended to stress the devices, both by voltage and by temperature so that weak devices are removed from the population which is shipped to the user of the devices, for example, removing the "infant mortality" portion of the reliability curve. On chip regulation of the bias voltage for the memory array, for example will preclude the direct application of power supply voltage to the capacitors. Hence another means of providing the burn-in voltage to the capacitors must be provided.
There are known current sources made with a field effect transistor and with a bias voltage source that is used to control the gate of the transistor. The reference or bias source voltage may be of the so called "bandgap" type. The term "bandgap" refers to the energy interval between the valance bands and the conduction bands of the semiconductor. Sources of this type use the known relationship of the dependency between the energy interval and the temperature to achieve compensation that makes the reference voltage as stable as possible as a function of temperature.
The voltage source of this bandgap generally has two diodes through which different current flows (or the same currents), but in this case the diodes are obligatorily ones with different junction surfaces, and a loop differential amplifier amplifying the voltage difference at the terminals and applying the diodes with current.
All bandgap references use the same underlying principle in that they generate a voltage proportional to the absolute temperature (V.sub.PTAT) which has a positive temperature coefficient. These bandgap voltages combine this voltage with a base-emitter voltage of the transistor, which has a negative temperature coefficient. When properly combined, for example with proper weighting, the two temperature coefficients cancel one another and results in a voltage that is fairly independent of temperature. This voltage is typically around 1.23 volts and is close to the bandgap voltage of silicon. Known bandgap architectures include those disclosed in U.S. Pat. Nos. 4,249,122, 4,447,784 and 3,887,863.
Furthermore, accelerated voltage testing is currently used in DRAM testing to eliminate early failure of devices and to guarantee that these devices are reliable. However, DRAM circuits also have generally a fixed life time and a device which has been over-stressed during testing will have a shorter useful lifetime. Hence, the accelerated voltage that is applied to the devices needs to be precise to prevent under stressing and over stressing. Since the testing are performed at both high and low temperatures, this accelerated voltage also needs to be constant over temperature variations. The prior art has not provided devices with this precise accelerated voltage at both high and low temperatures. As illustrated by FIG. 1, the accelerated voltage is designed to be 2.4 volts below the external voltage, nominally V.sub.EXT =8 volts. This accelerated voltage of 5.6 volts is generated by 3 P-channel transistors connected in series to provide a total voltage drop of 2.4 volts from the 8.0 volts V.sub.EXT supply. As illustrated in FIG. 2, a bias voltage V.sub.BIAS is converted to another voltage at node 108, the voltage at node 108 is applied to the gate of N-channel transistor 106 to induce a small current through the N-channel transistor 106 through the drain to source of the transistor 106. Each of the P-channel transistors 100, 102 and 104 are turned on and the voltage drop across each of these transistors is approximately above the threshold voltage of each of these transistors resulting in a voltage at node 110 to be approximately 5.6 volts. As a consequence of using three P-channel transistors to provide the voltage drop of 2.4 volts, any variation in the threshold voltage of the P-channel transistors 100, 102 and 104 is tripled Furthermore, any variation in threshold voltages of these P-channel transistors as a result of temperature variation is also tripled due to the series connection of these P-channels transistors. Thus, the circuit illustrated in FIG. 2 does not provide good temperature performance and good process performance.
FIG. 3 illustrates another circuit attempting to generate a proper burn-in reference voltage. The circuit of FIG. 3 generates a reference voltage through threshold voltage differences. The reference voltage is connected to a closed loop op-amp circuit to raise the voltage to a desired level.
P-channel transistors 120, 122 and 124 and N-channel transistor 125 are used to generate two biasing voltages, namely V.sub.BIASl and V.sub.BIASN from V.sub.EXT. These two biasing voltages V.sub.BISI and V.sub.BIASN are applied to the gates of to P-channel transistor 126 and N-channel transistor 129 respectively, to assure that the same reference current flows through P-channel transistors 126, 128 and 130 while the current through transistor 129 is doubled the original reference current, forcing the same current to flow through P-channel transistors 132 and 134. Thus, since P-channel transistors 128, 130, 132 and 134 respectively all have the same size and same current under the same electrical configuration, all these four transistors have the same V.sub.GST =V.sub.GS-V.sub.T. Since the four transistors are dioded connected, the source to drain voltage drop across each transistor is V.sub.DS =V.sub.GS =V.sub.GST +V.sub.T. Because transistors 132 and 134 have a larger V.sub.T, the voltage difference between V.sub.EXT and the voltage at node 142, the same as the voltage difference between the total voltage drop across transistors 132 and 134 and the total voltage drop across transistors 128 and 130 is two times (V.sub.T1 -V.sub.T2) where V.sub.T, is the threshold voltage of transistors 132 and 134 and V.sub.T2 is the threshold voltage of transistors 128 and 130. A closed loop op-amp is used as a multiplier to force the voltage on node 140, REFO, to be approximately the same as that on node 142 hence, V.sub.R1 =V.sub.EXT -V.sub.REFO and V.sub.EXT -REFO.apprxeq.2 * (V.sub.T -V.sub.T2). The Current through R.sub.1 and R.sub.2 is (V.sub.EXT -REFO/R1. The voltage drop across R.sub.1 and R.sub.2 is equal to current R.sub.1 .times.(R.sub.1 +R.sub.2). Therefore the voltage drop is equal to ##EQU1## Therefore, the output voltage of the multiplier is V.sub.REFBI, where V.sub.REFBI equals V .sub.EXT -((R.sub.2 +R.sub.1)/R.sub.1) * 2* (V.sub.T1 -V.sub.T2). Thus by adjusting the ratio of resistance R1, of resistor 136 and the resistance R2 of resistor 138 a desired V.sub.REFBI can be obtained. A serious disadvantage of the above approach is the need of a dedicated reference voltage calling for additional masks to produce transistors with different threshold voltages and additional testing of this circuit and on-chip trying of resistors 136 or 138.